Thin film transistor and manufacturing method thereof, and active matrix display device and manufacturing method thereof

ABSTRACT

A method of manufacturing a thin film transistor (TFT) which is manufactured such that source and drain electrodes directly contact source and drain regions without contact holes.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.2001-10842, filed on Mar. 2, 2001, in the Korean Industrial PropertyOffice, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor (TFT), and moreparticularly, to a method of manufacturing the same. Also, the presentinvention relates to an active matrix display device and a manufacturingmethod thereof.

2. Description of the Related Art

As a type of flat panel display device, an organic electro-luminesence(EL) display device is being watched with keener interest than any otherdisplay device, such as a cathode ray tube (CRT) and a liquid crystaldisplay (LCD) device. In comparison to the CRT having the same screensize, the organic EL display device is thin, lightweight, and has lowerpower consumption. Since the organic EL display device emits light byitself, it does not require a back light device. Therefore, alightweight, small-sized and compact display device can be achieved. Inaddition, the organic EL display device has an advantage in that thereis no limitation to a viewing angle. As such, organic EL display devicehaving a thin film transistor (TFT) as a switching element is beingactively developed.

FIG. 1 is a cross-sectional view illustrating a conventional TFT. Aprocess of manufacturing the conventional TFT is described below withreference to FIG. 1. First, a buffer layer 11 is formed on a transparentinsulating substrate (“substrate”) 10. The substrate 10 is a transparentglass substrate or a transparent plastic substrate. A polycrystallinesilicon layer is deposited on the buffer layer 11 and then patterned toform a semiconductor layer 12.

Then a first insulating layer 13 is deposited over the Whole surface ofthe substrate 10 as well as covering the semiconductor layer 12. Thefirst insulating layer 13 serves as a gate insulating layer. A firstmetal layer is deposited on the first insulating layer 13 over thesemiconductor layer 12 and then patterned to form a gate electrode 14.Using the gate electrode 14 as a mask, a low-density impurity, such as an-type or a p-type low-density impurity, is ion-implanted into both endportions of the semiconductor layer 12 to form low-density source anddrain regions 15-1 and 15-2.

Thereafter, the gate electrode 14 is anodized to form an anodizing layer16 surrounding the gate electrode 14. For example, the anodizing layeris made of Al₂O₃, if the gate electrode is made of Al. A high-densityimpurity having the same conductivity as the low-density source anddrain regions 15-1 and 15-2 is ion-implanted into portions of thelow-density source and drain regions 15-1 and 15-2 that are not coveredwith the anodizing layer 16 to form source and drain regions 17-1 and17-2.

Subsequently, a second insulating layer 18 is deposited over the wholesurface of the substrate 10 and then patterned to form first and secondcontact holes 19-1 and 19-2. The first contact hole 19-1 is formed at alocation corresponding to a portion of the source region 17-1, and thesecond contact hole 19-2 is formed at a location corresponding to aportion of the drain region 17-2. The second insulating layer 18 servesas an interlayer insulator.

Finally, a second metal layer is deposited on the interlayer insulator18 and patterned to form source and drain electrodes 20-1 and 20-2. Thesource and drain electrodes 20-1 and 20-2 contact the source and drainregions 17-1 and 17-2 through the first and second contact holes 19-1and 19-2, respectively. Therefore, the TFT having a lightly doped drain(LDD) structure is completed.

In order to manufacture a TFT having an off-set structure, a process ofion-implanting the low-density impurity is omitted.

The manufacture of the TFT having the LDD structure or the off-setstructure requires four mask processes. A first mask forms thesemiconductor layer 12. A second mask forms the gate electrode 14. Athird mask forms the contact holes 19-1 and 19-2. A fourth mask formsthe source and drain electrodes 20-1 and 20-2. Thus makes themanufacture of a conventional TFT very complicated and costly.

Also, the conventional method of manufacturing the TFT uses theanodizing layer 16 other than a photoresist pattern, and thus forms theLDD region in a self-aligning manner. However, an additional apparatusis necessary to anodize the gate electrode 14 and form the anodizinglayer 16, leading to a very complicated manufacturing process.

In addition, since the source and drain electrodes 20-1 and 20-2 contactthe high-density source and drain regions 17-1 and 17-2, a contactresistance increases, thereby degrading electric characteristics of theTFT.

FIG. 2 is a cross-sectional view illustrating a conventional organic ELdisplay device having the TFT of FIG. 1 as a switching element.Subsequent to the process of manufacturing the TFT shown in FIG. 1, athird insulating layer 21 is formed over the whole surface of thesubstrate 10 so as to cover the source and drain electrodes 20-1 and20-2. The third insulating layer 21 serves as a passivation layer. Thepassivation layer 21 includes a through hole 22 at a locationcorresponding to a portion of either of the source and drain electrodes20-1 and 20-2. In FIG. 2, the through hole 20 is formed on a portion ofthe drain electrode 20-2.

Then, a transparent conductive material is deposited and patterned toform a pixel electrode 23. The pixel electrode 23 contacts the drainelectrode 20-2 through the through hole 22 and serves as an anodeelectrode 23.

Subsequently, a planarization layer 24 is formed over the whole surfaceof the substrate 10. The planarization layer 24 has an opening portion25. The opening portion 25 exposes a portion of the anode (pixel)electrode 23.

Next, an organic EL layer 26 is formed on the exposed portion of theanode electrode 23. Finally, the organic EL display device is completedwhen a cathode electrode 27, which covers the organic EL layer 26.

In order to manufacture the organic EL display device shown in FIG. 2,three mask processes are required in addition to the four mask processesrequired to manufacture the TFT. A fifth mask forms the through hole 22.A sixth mask forms the anode electrode 23. A seventh mask forms theopening portion 25. These additional processing operations and timecomplicate the manufacturing process of the organic EL display device.As a result, the manufacturing yield is low, and the production cost ishigh.

SUMMARY OF THE INVENTION

To overcome the above and other problems, it is an object of the presentinvention to provide a thin film transistor and an active matrix crystaldisplay device having a simplified manufacturing process leading to ahigh manufacturing yield and a low production cost.

It is another object of the present invention to provide a thin filmtransistor and an active matrix display device having excellent electriccharacteristics.

Additional objects and advantages of the invention will be set forth inpart in the description which follows and, in part, will be obvious fromthe description, or may be learned by practice of the invention.

To achieve the above and other objects of the present invention, thereis provided a method of manufacturing a thin film transistor (TFT),comprising forming a semiconductor layer on an insulating substrateusing a first mask, forming a gate insulating layer over the wholesurface of the substrate, forming a gate electrode having a cappinglayer thereon using a second mask, forming spacers on both side wallportions of the gate electrode and the capping layer over the gateinsulating layer while exposing both end portions of the semiconductorlayer, forming high-density source and drain regions by ion-implanting ahigh-density impurity into the exposed portions of the semiconductorlayer, and forming source and drain electrodes without contact holes,using a third mask to directly contact the high-density source and drainregions, respectively.

According to an aspect of the invention, the forming of the spacersincludes depositing an insulating layer over the whole surface of thesubstrate and patterning the insulating layer and the gate insulatinglayer to form the spacers so as to expose both end portions of thesemiconductor layer, where the insulating layer for the spacers and thecapping layer is made of an oxide layer or a nitride layer, and thehigh-density source and drain regions are formed at a predetermineddistance from the gate electrode so as to have the semiconductor layerwith offset regions formed under the spacers.

According to another aspect of the invention, the method ofmanufacturing the TFT further includes forming low-density source anddrain regions by ion-implanting a low-density impurity having the sameconductivity type as the high-density impurity into the semiconductorlayer after the forming of the gate electrode, so as to have thesemiconductor layer with LDD regions formed under the spacers, where thecapping layer serves as an impurity barrier to shield the gate electrodefrom being ion-implated during the process of ion-implanting thelow-density impurity.

According to yet another aspect of the invention, the method ofmanufacturing the TFT further includes forming silicide layers on theexposed portions of the semiconductor layer after the forming of thespacers.

According to another embodiment of the present invention, a thin filmtransistor (TFT) includes a semiconductor layer formed on an insulatingsubstrate, a gate insulating layer formed on the semiconductor layer soas to expose both end portions of the semiconductor layer, a gateelectrode formed on the gate insulating layer, a capping layer formed onthe gate electrode, spacers formed on the gate insulating layer and onboth side wall portions of the gate electrode and the capping layer,high-density source and drain regions formed at the exposed end portionsof the semiconductor layer beyond the spacers, and source and drainelectrodes which directly contact the high density source and drainregions, respectively.

According to an aspect of the invention, the semiconductor layer hasoff-set regions formed under the spacers, the semiconductor layer haslow-density source and drain regions having the same conductivity as thehigh-density source and drain regions under the spacers so as to havethe semiconductor layer with LDD regions under the spacers.

According to another aspect of the invention, the capping layer and thespacers are made of an oxide layer or a nitride layer, and the TFTfurther comprises silicide layers formed both between the sourceelectrode and the high-density source region, and between the drainelectrode and the high-density drain region.

According to a further aspect of the present invention, a method ofmanufacturing an active matrix display device includes forming asemiconductor layer on an insulating substrate using a first mask,forming a first insulating layer over the whole surface of thesubstrate, forming a gate electrode having a capping layer thereon usinga second mask, forming spacers on both side wall portions of the gateelectrode and the capping layer over the first insulating layer whileexposing both end portions of the semiconductor layer, forminghigh-density source and drain regions by ion-implanting a high-densityimpurity into the exposed portions of the semiconductor layer, formingsource and drain electrodes without contact holes using a third mask, soas to directly contact the high-density source and drain regions,respectively, forming a second insulating layer over the whole surfaceof the substrate, forming an opening portion by etching the secondinsulating layer using a fourth mask and exposing either a portion ofthe source electrode or a portion of the drain electrode, and forming apixel electrode on the second insulating layer to contact an areaexposed by the opening portion.

According to a further embodiment of the present invention, an activematrix display device includes a semiconductor layer formed on aninsulating substrate, a gate insulating layer formed on thesemiconductor layer so as to expose both end portions of thesemiconductor layer, a gate electrode formed on the gate insulatinglayer, a capping layer formed on the gate electrode, spacers formed onthe gate insulating layer and on both side wall portions of the gateelectrode and the capping layer, high-density source and drain regionsformed to the exposed end portions of the semiconductor layer beyond thespacers, source and drain electrodes which directly contact the highdensity source and drain regions, respectively, a planarization layerhaving an opening portion which exposes either a portion of the sourceelectrode or a portion of the drain electrode, and a pixel electrodeformed on the planarization layer which contacts an area exposed by theopening portion.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the present invention willbecome more apparent and more readily appreciated from the followingdescription of the preferred embodiments, taken in conjunction with theaccompanying drawings of which:

FIG. 1 is a diagram illustrating a cross-sectional view of aconventional TFT;

FIG. 2 is a diagram illustrating a cross-sectional view of aconventional organic EL display device having the TFT of FIG. 1 as aswitching element;

FIGS. 3A to 3L are diagrams of cross-sectional views illustrating amethod of manufacturing a TFT according to an embodiment of the presentinvention;

FIG. 4 is a diagram illustrating a plane view of a portion of an organicEL display device according to the present invention;

FIGS. 5A to 5F are diagrams of cross-sectional views taken along lineV-V of FIG. 4 illustrating a method of manufacturing a organic ELdisplay device according to another embodiment of the present inventionhaving the TFT of FIG. 3L;

FIG. 6 is a diagram illustrating a cross-sectional view taken along lineVI-VI of FIG. 4 illustrating the organic EL display device according tothe present invention having a switching TFT;

FIG. 7 is a diagram illustrating a cross-sectional view of yet anotherembodiment of the present invention with two opening portions formed toexpose a portion of a buffer layer and a portion of a drain electrode;and

FIG. 8 is a diagram illustrating a cross-sectional view of still anotherembodiment of the present invention with a opening portion formed toexpose a portion of a drain electrode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to the like elementsthroughout. The embodiments are described below in order to explain thepresent invention by referring to the figures.

FIGS. 3A to 3L are cross-sectional views illustrating a thin filmtransistor (TFT) according to an embodiment of the present invention.FIG. 3A shows a buffer layer 31 formed on a transparent substrate 30. Apolycrystalline silicon layer 32 is deposited on the buffer layer 31 andthen patterned using a first mask to form a semiconductor layer 33 asshown in FIG. 3B.

In order to form the semiconductor layer 33, an amorphous silicon layercan be deposited and then be crystallized through, for example, a laserannealing process to form the polycrystalline silicon layer 32. Thepolycrystalline silicon layer 32 is patterned to form the semiconductorlayer 33 in a form of an island.

The buffer layer 31 is an oxide layer, such as SiO₂, and serves toshield impurities, such as a sodium ion, from being diffused from thesubstrate 30 into the semiconductor layer 33.

FIGS. 3C and 3D show that a first insulating layer 34, a first metallayer 35 and a second insulating layer 36 are sequentially depositedover the whole surface of the substrate 30 so as to cover thesemiconductor layer 33. The first insulating layer 34 serves as a gateinsulating layer. The first and second insulating layers 34 and 36 aremade of an oxide layer (e.g., SiO₂) or a nitride layer (e.g., SiN_(x)).

The first metal layer 35 and the second insulating layer 36 arepatterned using a second mask to form a gate electrode 37 and a cappinglayer 38 over the semiconductor layer 33.

FIG. 3E shows that a low-density impurity, such as a n-type or a p-typelow-density impurity, is then ion-implanted into both end portions ofthe semiconductor layer 33 using the gate electrode 37 as a mask to formlow-density source and drain regions 39-1 and 39-2. At this time, thecapping layer 38 shields the low-density impurity from beingion-implanted into the gate electrode 37, thereby preventing defects,such as a hillock or a crack, in the gate electrode 37.

FIGS. 3F and 3G show that a third insulating layer 40 is deposited overthe whole surface of the substrate 30. The third insulating layer 40 isthen etched-back to form spacers 41 on both side wall portions of thegate electrode 37 and the capping layer 38 so that the gate electrode 37is perfectly insulated by the capping layer 38 and the spacers 41. Anoxide layer or a nitride layer is used as the third insulating layer 40.At the same time, the first insulating layer 34 is etched to expose endportions of the low-density source and drain regions 39-1 and 39-2.

Next, FIGS. 3H and 3I show that a second metal layer 42 is depositedover the whole surface of the substrate 30 and then reacted with siliconof the semiconductor layer 33 through a silicide process to formsilicide layers 43-1 and 43-2 on the exposed portions of the low-densitysource and drain regions 39-1 and 39-2, respectively. The second metallayer 42 is made of a refractory metal such as Cr or Ni. The portions ofthe second metal layer 42 that do not react with the silicon areremoved.

FIG. 3J shows that by using the gate electrode 37, the capping layer 38and the spacers 41 as a mask, a high-density impurity having the sameconductivity type as the source and drain regions 39-1 and the 39-2 ision-implanted into the exposed portion of the low-density source anddrain regions 39-1 and 39-2 in a self-aligning manner to formhigh-density source and drain regions 44-1 and 44-2. The TFT of the FIG.3J has an LDD structure.

Since the high-density impurity is ion-implanted into the semiconductorlayer 33 through the silicide layers 43-1 and 43-2, the semiconductorlayer 33 is protected by the suicide layers 43-1 and 43-2, therebyminimizing damage to the semiconductor layer 33 due to theion-implantation.

Finally, FIGS. 3K and 3L show that a third metal layer 45 is depositedover the whole surface of the substrate 30 and then patterned using athird mask to form source and drain electrodes 46-1 and 46-2. The sourceand drain electrodes 46-1 and 46-2 directly contact the high-densitysource and drain regions 44-1 and 44-2 through the silicide layers 43-1and 43-2, respectively and without using contact holes.

In order to form an off-set structure instead of an LDD structureaccording to a further embodiment of the present invention, a process ofion-implanting a low-density impurity of FIG. 3E can be omitted.

According to an embodiment of the present invention, the three maskprocesses are used to simplify the manufacture of the TFT. For example,since the high-density source and drain regions 44-1 and 44-2 are formedin a self-aligning manner using the spacers 41 as a mask, an additionalanodizing process is not required. Also, since the source and drainelectrodes 46-1 and 46-2, without contact holes, directly contact thehigh-density source and drain regions, one of the masking processes canbe omitted.

In addition, since the silicide layers 43-1 and 43-2 are formed betweenthe high-density source and drain regions 44-1 and 44-2 and the sourceand drain electrodes 46-1 and 46-2, respectively, a contact resistancecan be reduced. Furthermore, the silicide layers 43-1 and 43-2 serve asan etching barrier for the source and drain electrodes to improve anetching selectivity, and also serve to minimize the damage to thesemiconductor layer 33 due to the ion-implantation, since thehigh-density impurity is ion-implanted through the silicide layers 43-1and 43-2.

The TFT according to the embodiment of the present invention has an LDDstructure or an off-set structure, and improved electriccharacteristics. For example, since an off current is reduced, an on/offcurrent ratio can be improved.

In addition, since the gate electrode 37 is insulated from the sourceand drain electrodes 46-1 and 46-2 by the capping layer 38 and thespacers 41, a sufficient insulation between the gate electrode 37 andthe source and drain electrodes 46-1 and 46-2 can be secured without theinterlayer insulator 18 having contact holes 19-1 and 19-2 that providea contact between the source and drain regions 17-1 and 17-2 and thesource and drain electrodes 20-1 and 20-2 as shown in FIG. 1.

An organic EL display device includes a transparent insulatingsubstrate, signal lines and a pixel connected to the signal lines. FIG.4 is a plan view illustrating a portion of an organic EL display device100 according to an embodiment of the present invention. A gate line 120applies a signal to turn on or off TFTs of a pixel 160. A data line 130applies a data voltage to the pixel 160. A power supply line 140 isarranged in a parallel direction to the data line 130 and applies anelectrical power to the pixel 160 while the organic EL display device100 is driven.

Each of the pixel 160 includes a switching TFT 170, a storage capacitor180, a driving TFT 200, and an organic EL element 300. The switching TFT170 is arranged at an intersection of the gate line 120 and the dataline 130 and is driven by a signal applied from the gate line 120. Theswitching TFT 170 has a semiconductor layer 172, a gate electrode 174, asource electrode 176, and a drain electrode 178. The gate electrode 174extends from the gate line 120, and the source electrode 176 extendsfrom the data line 130. The source and drain electrodes 176 and 178directly contact the semiconductor layer 172 in which high-densitysource and drain regions (not shown) are formed, respectively, withoutcontact holes.

The storage capacitor 180 is connected between the switching TFT 170 andthe corresponding power supply line 140 and serves to maintain dataapplied from the data line 130 so that the organic EL display device 100can maintain the data during one frame. The storage capacitor 180includes first and second capacitor electrodes 182 and 184 with adielectric layer (not shown) interposed therebetween. The firstcapacitor electrode 182 is connected to the drain electrode 178 of theswitching TFT 170 through a connection pad 315 (see FIG. 6). The secondcapacitor electrode 184 extends from the power supply line 140. In otherwords, the drain electrode 178 of the switching TFT 170 is connected tothe connection pad 315 through a contact hole 261, and the firstcapacitor electrode 182 is connected to the connection pad 315 through acontact hole 262, whereby the switching TFT 170 is electricallyconnected to the capacitor 180.

The first capacitor electrode 182 is made of the same material as thegate line 120 and the gate electrode 174, and is formed at the same timeas the gate line 120 and the gate electrode 174. The second capacitorelectrode 184 is made of the same material as the source and drainelectrode 176 and 178 and the power supply line 140, and is formed atthe same time as the source and drain electrode 176 and 178 and thepower supply line 140.

The driving TFT 200 is connected to the power supply line 140 and thestorage capacitor 180, and serves to drive the organic EL element 300.The driving TFT 200 includes a semiconductor layer 210, a gate electrode220, a source electrode 250, and a drain electrode 255. The gateelectrode 220 of the driving TFT 200 extends from the first capacitorelectrode 182, and the source electrode 250 of the driving TFT 200extends from the power supply line 140. The source and drain electrodes250 and 255 directly contact the semiconductor layer 210, withoutcontact holes. The drain electrode 255 of the driving TFT 200 contactsan anode 310 of the organic EL element 300 through an opening portion267 (shown in FIGS. 5C-5E). As such, the driving TFT 200 is electricallyconnected to the organic EL element 300.

A process of manufacturing the organic EL display device 100 accordingto an embodiment of the invention is explained in detail below withreference to FIGS. 5A to 5F and 6. FIGS. 5A to 5F are cross-sectionalviews taken along line V-V of FIG. 4, and FIG. 6 is a cross-sectionalview taken along line VI-VI of FIG. 4.

FIG. 5A shows that a buffer layer 202 is formed on a transparentsubstrate 110. The buffer layer 202 is made of, for example, SiO₂. Apolycrystalline silicon layer is deposited on the buffer layer 202 andthen patterned using a first mask to form a semiconductor layer 210 of adriving TFT 200. At this time, a semiconductor layer 172 of a switchingTFT 170 (see FIG. 6) is formed at the same time as the semiconductorlayer 210 of the switching TFT 200.

A gate insulating layer 215 is formed over the whole surface of thesubstrate 110 using a second mask, and a gate electrode 220 and acapping layer 225 are formed on the gate insulating layer 215 over thesemiconductor layer 210. At the same time, a gate electrode 174 and acapping layer 225 of the switching TFT 170, a first capacitor electrode182 and a dielectric layer 183 (see FIG. 6) are formed. The gate line120 (see FIG. 4) is formed at the same time as the gate electrode 220.The gate insulating layer 215 and the capping layer 225 are made of, forexample, SiO₂ or SiN_(x).

Then, a low-density impurity, such as an n-type or a p-type low-densityimpurity, is ion-implanted into both end portions of the semiconductorlayer 210 using the gate electrode 220 as a mask to form low-densitysource and drain regions 214-1 and 214-2 of the driving TFT 200.

At the same time, a low-density impurity is ion-implanted into both endportions of the semiconductor layer 172 using the gate electrode 174 asa mask to form low-density source and drain regions 173-1 and 173-2 ofthe switching TFT 170 (see FIG. 6).

The capping layers 225 of FIG. 5A and FIG. 6 serve as impurity barriersthat shield the low-density impurity from being ion-implanted into thegate electrodes 174 and 220. Also, the dielectric layer 183 of FIG. 6serves to shield the low-density impurity form being ion-implanted intothe first capacitor electrode 182. Referring to FIGS. 5A and 6, aportion of the semiconductor layer 172 between the low-density sourceand drain regions 173-1 and 173-2 and a portion of the semiconductorlayer 210 between the low-density source and drain regions 214-1 and214-2 serve as channel areas of the TFTs 170 and 200, respectively.

Subsequently in FIG. 5A, an insulating layer for spacers is depositedover the whole surface of the substrate 110 and then etched-back to formspacers 230 on both side wall portions of the gate electrode 220 and thecapping layer 225. Thus, the gate electrode 220 is perfectly insulatedby the capping layer 225 and the spacers 230. An oxide layer or anitride layer is used as the insulating layer for spacers. The gateinsulating layer 215 is also etched to expose end portions of thelow-density source and drain regions 214-1 and 214-2.

At the same time, spacers 230 (see FIG. 6) are also formed on both sidewall portions of the gate electrode 174 of the switching TFT and of thefirst capacitor electrode 182. And, when the gate insulating layer 215(FIG. 6) of the switching TFT 170 is etched, end portions of thelow-density source and drain regions 173-1 and 173-2 are exposed.

Next, FIG. 5A and FIG. 6 show that silicide layers 240 are formed on theexposed portions of the low-density source and drain regions 214-1 and214-2 and on the exposed portions of the low-density source and drainregions 173-1 and 173-2, respectively.

Subsequently, using the gate electrode 220 and the spacers 230 as amask, a high-density impurity having the same conductivity as thelow-density source and drain regions 214-1 and 214-2 is ion-implantedinto the exposed portion of the low-density source and drain regions214-1 and 214-2 in a self-aligning manner to form high-density sourceand drain regions 216-1 and 216-2.

At the same time, high-density source and drain regions 175-1 and 175-2of the switching TFT (see FIG. 6) are formed under the silicide layers240. The TFTs 170 and 200 of FIG. 5A and FIG. 6 have an LDD structure.

Since the high-density impurity is ion-implanted into the semiconductorlayers 172 and 210 through the silicide layers 240, the semiconductorlayers 172 and 210 are protected by the silicide layers 240, therebyminimizing damage to the semiconductor layers 172 and 210 due to theion-implantation.

Finally in FIG. 5A, a metal layer for source and drain electrodes isdeposited over the whole surface of the substrate 110 and then patternedusing a third mask to form the source and drain electrodes 250 and 255.The source and drain electrodes 250 and 255 directly contact thehigh-density source and drain regions 216-1 and 216-2 through thesilicide layers 240, respectively, and without the contact holes 19-1and 19-2 shown in FIG. 1.

At the same time, the source and drain electrodes 176 and 178 of theswitching TFT 170 (see FIG. 6) are formed to directly contact thehigh-density source and drain regions 175-1 and 175-2 through thesuicide layers 240, respectively. Even though not shown, the data line130 and the power supply line 140 are also formed at the same time(referring to FIG. 4).

In order to form an off-set structure instead of an LDD structure, aprocess of ion-implanting a low-density impurity can be omitted.

FIGS. 5B and 5C show that a planarization layer 260 is formed over thewhole surface of the substrate 110. The planarization layer 260 isetched using a fourth mask to form an opening portion 267. The openingportion 267 exposes an end portion of the drain electrode 255 of thedriving TFT 200 and a portion of the buffer layer 202.

The contact holes 261 and 262 (See FIG. 6) are formed on a portion ofthe drain electrode 178 of the switching TFT 170 and a portion of thefirst capacitor electrode 182 when the opening portion 267 is formed.

FIGS. 5D and 5E show that a transparent conductive material layer 310 ais deposited over the whole surface of the substrate 110 and thenpatterned using a fifth mask to form a pixel electrode 310 that contactsthe drain electrode 255 through the opening portion 267. The pixelelectrode 310 is made of a transparent conductive material such asindium tin oxide (ITO) or indium zinc oxide (IZO) and is used as ananode electrode of an organic EL element 300 (see FIG. 4).

A connection pad 315 (see FIG. 6) is formed to electrically connect thedrain electrode 178 and the first capacitor electrode 182 through thecontact holes 261 and 262.

Alternatively, in order to contact the pixel electrode 310 and the drainelectrode 255 instead of using the method shown in FIG. 5C according toanother embodiment of the invention shown in FIG. 7, two openingportions 267 and 267 a are formed to expose a portion of the drainelectrode 255 and a portion of the buffer layer 202, respectively.Otherwise, according to yet another embodiment of the invention shown inFIG. 8, one opening portion 267 that exposes a portion of the drainelectrode 255 can be formed.

However the opening portion 267 is formed, FIG. 5F shows that an organicEL layer 320 and a cathode electrode 330 are sequentially formed on theanode electrode 310 and the planarization layer 260. The organic ELlayer 320 and the cathode electrode 330 are not formed over the storagecapacitor 180 and the TFTs 170 and 200 (see FIG. 4 and FIG. 6). Thecathode electrode 330 is preferably made of a metal having a lower workfunction than the anode electrode 310.

Even though not shown, the organic EL layer 320 includes a hole transferlayer, a light-emitting layer and an electron transfer layer. The holetransfer layer transfers holes from the anode electrode 310 to thelight-emitting layer, and the electron transfer layer transferselectrons from the cathode electrode 330 to the light-emitting layer, sothat holes and electrons are recombined to emit light. That is, holesand electrons are recombined so that organic molecules that constitutethe light-emitting layer are excited, to emit excitons, and the emittedexcitons become inactivated, whereupon light radiates from thelight-emitting layer.

As described above, the active matrix display device according to theembodiments of the present invention have the following advantages.Since the source and drain electrodes directly contact the source anddrain regions without contact holes, the number of mask processes isreduced, thereby simplifying a manufacturing process. Furthermore, sinceonly five mask processes are required to manufacture the active matrixdisplay device, the overall manufacturing process is simplified, leadingto a higher manufacturing yield and a lower production cost. Also, sincethe capping layer is formed on the gate electrode of the TFT while anion-implanting process is performed to form the low-density source anddrain regions, damage to the gate electrode is prevented. In addition,due to the silicide layers respectively formed between the source anddrain regions and the source and drain electrodes, a contact resistanceis reduced, leading to a high reliability. In addition, since an LDDregion or an off-set region is formed in a self-aligning manner throughthe spacers formed on both side wall portions of the gate electrode andthe capping layer, the manufacturing process is again simplified, andthe electric characteristics such as an on/off current ratio areimproved.

Although a few embodiments of the present invention have been shown anddescribed, it will be appreciated by those skilled in the art thatchanges may be made in these embodiments without departing from theprinciples and spirit of the invention, the scope of which is defined inthe appended claims and their equivalents.

1. A thin film transistor (TFT), comprising: a substrate; asemiconductor layer formed over said substrate having end portions; afirst insulating layer disposed on said semiconductor layer so as toexpose end portions of said semiconductor layer; a gate electrode formedover said first insulating layer; a capping layer formed over said gateelectrode; spacers formed over said first insulating layer and directlycontacting both side wall portions of said gate electrode and saidcapping layer; high-density source and drain regions formed at the endportions of said semiconductor layer exposed beyond said spacers, thehigh-density source and drain regions being spaced apart from the gateelectrode and the capping layer; low-density source and drain regionshaving a same conductivity as said high-density source and drain regionsformed at regions of said semiconductor layer under said spacers betweenthe gate electrode and the high-density source and drain regions,thereby providing said semiconductor layer with lightly doped drain(LDD) regions under said spacers; and source and drain electrodes whichrespectively contact said high-density source and drain regions withoutcontact holes.
 2. The TFT of claim 1, wherein said first insulatinglayer, said capping layer and said spacer are one of an oxide layer anda nitride layer.
 3. The TFT of claim 1, further comprising a silicidelayer formed between said source electrode and said high-density sourceregion and a silicide layer formed between said drain electrode and saidhigh-density drain region.
 4. The TFT of claim 3, wherein said silicidelayers comprise a refractory metal.
 5. The TFT of claim 1, wherein saidhigh-density source and drain regions and said low-density source anddrain regions extend through an entire thickness of said semiconductorlayer.
 6. The TFT of claim 1, wherein said high-density source and drainregions are formed at entireties of the end portions of saidsemiconductor layer exposed beyond said spacers; and wherein saidlow-density source and drain regions having a same conductivity as saidhigh-density source and drain regions are formed at entireties ofregions of said semiconductor layer entirely under said spacers betweenthe gate electrode and the high-density source and drain regions,thereby providing said semiconductor layer with lightly doped drain(LDD) regions entirely under said spacers.
 7. The TFT of claim 1,wherein the source and drain electrodes do not contact the high-densitysource and drain regions via any electrode material filling any contactholes.
 8. The TFT of claim 1, wherein the capping layer and the spacersare separate layers.
 9. The TFT of claim 1, wherein the source and drainelectrodes do not contact the capping layer; and wherein the source anddrain electrodes do not contact the spacers.
 10. The TFT of claim 1,wherein: the source and drain electrodes do not contact the high-densitysource and drain regions via any electrode material filling any contactholes; the source and drain electrodes do not contact the capping layer;and the source and drain electrodes do not contact the spacers.
 11. TheTFT of claim 10, wherein the capping layer and the spacers are separatelayers.
 12. An active matrix display device, comprising: a substrate; asemiconductor layer having end portions formed over said substrate; afirst insulating layer formed over said semiconductor layer so as toexpose end portions of said semiconductor layer; a gate electrode formedover said first insulating layer; a capping layer formed over said gateelectrode; spacers formed over said first insulating layer and directlycontacting both side wall portions of said gate electrode and saidcapping layer; high-density source and drain regions formed atentireties of the end portions of said semiconductor layer exposedbeyond said spacers; low-density source and drain regions having a sameconductivity as said high-density source and drain regions formed atentireties of off-set regions of said semiconductor layer entirely undersaid spacers, thereby providing said semiconductor layer with lightlydoped drain (LDD) regions entirely under said spacers; source and drainelectrodes which respectively contact said high-density source and drainregions without contact holes; a planarization layer having an openingportion which exposes a portion of one of said source and drainelectrodes; and a pixel electrode formed on the planarization layer, thepixel electrode contacting the portion of the one of the source anddrain electrodes through the opening portion.
 13. The active matrixdisplay device of claim 12, further comprising a silicide layer formedbetween said source electrode and said high-density source region and asilicide layer formed between said drain electrode and said high-densitydrain region.
 14. The active matrix display device of claim 12, furthercomprising an organic electro-luminescence (EL) layer and a cathodeelectrode sequentially formed on a first predetermined area of saidpixel electrode and on a second predetermined area of said planarizationlayer.
 15. The active matrix display device of claim 12, wherein saidhigh-density source and drain regions and said low-density source anddrain regions extend through an entire thickness of said semiconductorlayer.
 16. The active matrix display device of claim 12, wherein thesource and drain electrodes do not contact the high-density source anddrain regions via any electrode material filling any contact holes. 17.The active matrix display device of claim 12, wherein the capping layerand the spacers are separate layers.
 18. The active matrix displaydevice of claim 12, wherein the source and drain electrodes do notcontact the capping layer; and wherein the source and drain electrodesdo not contact the spacers.
 19. The active matrix device of claim 12,wherein: the source and drain electrodes do not contact the high-densitysource and drain regions via any electrode material filling any contactholes; the source and drain electrodes do not contact the capping layer;and the source and drain electrodes do not contact the spacers.
 20. Theactive matrix display device of claim 19, wherein the capping layer andthe spacers are separate layers.